Computer systems use memory devices, such as dynamic random access memory (“DRAM”) devices, to store instructions and data that are accessed by a processor. These memory devices are normally used as system memory in a computer system. In a typical computer system, the processor communicates with the system memory through a processor bus and a memory controller. The processor issues a memory request, which includes a memory command, such as a read command, and an address designating the location from which data or instructions are to be read. The memory controller uses the command and address to generate appropriate command signals as well as row and column addresses, which are applied to the system memory. In response to the commands and addresses, data are transferred between the system memory and the processor. The memory controller is often part of a system controller, which also includes bus bridge circuitry for coupling the processor bus to an expansion bus, such as a PCI bus.
A memory system 10 typically used in a computer system is shown in FIG. 1. The memory system 10 includes a memory controller 14 coupled to several memory modules 20a, b . . . n through a bus system 24. The bus system 24 typically includes an address bus 26 a command bus 28 and a bi-directional data bus 30. However, other conventional memory systems may use bus systems 24 having other configurations, such as a combined address bus 26 and command bus 28. In any case, each of the memory modules 20 includes several memory devices 34, such as DRAM devices, mounted on an insulative substrate 36. Conductive leads 38 are fabricated on the substrate 36 to couple the memory devices 34 to the buses 26-30. The conductive leads 38 typically couple the memory devices 34 to all of the buses 26-30 in parallel, although some of the lines in the command bus 28, such as chip select lines, may be coupled to the memory devices 34 in fewer than all of the memory modules 20.
In operation, the memory controller 14 applies row and column addresses through the address bus 26 and command signals to the command bus 28 to read data from or write data to the memory devices 34. In the event of a write memory access, there are also coupled from the memory controller 14 to the memory devices 34. In the event of a read memory access, data are coupled from the memory devices 34 to the memory controller 14. Although address, command and write data signals are applied to the memory devices 34 and all of the memory modules 20, a chip select signal or other similar signal selects the memory devices 34 on only one of the memory modules 20 for the memory access.
The memory modules 20 shown in FIG. 1 are normally configured for a particular data format. For example, sixteen memory devices 34 may be included in the memory module 20, and each memory device 34 may couple a single bit of data to and from the memory controller 14. In such case, each of the memory modules 20 will input and output data in 16-bit words. Alternatively, the memory devices 34 may be divided into two groups or “ranks” each of which are individually accessed by, for example, being enabled by separate chip select signals. In such case, if each memory device 34 couples a single bit of data to and from the memory controller 14, the memory module 20 will output data in 8-bit bytes. By way of further example, the memory devices 34 on each memory module may be individually accessed, and each memory device 34 may couple 8 bits of data to and from the memory controller 14. In such case, each memory module 20 will output data in 8-bit bytes. Other data formats used in conventional memory systems will be apparent to one skilled in the art.
The selection of a data format controls not only the size of the data word coupled to and from each memory module 20, but it also controls the effective size of the memory that may be addressed in each module 20. More specifically, assume each memory module 20 includes eight memory devices 34 each of which has an 8-bit data bus and one million addressable locations. Each memory device 34 thus has a capacity of 1 MB so that the total size of the memory module 20 is 8 MB. Each of the memory devices 34 may be individually addressed to interface with an 8-bit data bus so that there are 8 million addresses in the address space. Alternatively, all of the memory devices 34 may be simultaneously addressed to interface with a 64-bit data bus so that there are 1 million addresses in the address space. The memory devices 34 may also be operated in two ranks to interface with a 32-bit data bus with an address space of 4 million addresses. In all of these cases, the total memory capacity of the memory module 20 is 8 MB. However, in each of these cases the data bandwidth, i.e., the rate at which data bits are coupled through the data bus, and the number of memory addresses, i.e., the depth of the memory module 20, vary. The memory bandwidth and memory depth are thus trade-offs of each other.
In conventional memory systems, the memory bandwidth and memory depth are selected based the bandwidth and depth desired for a specific application. For example, a first data format may be used for a system in which maximizing bandwidth is important, such as a memory system used in a video graphics card. However, a second data format may be used in a system in which maximizing memory depth is important, such as in a database system. Unfortunately, the memory system must be optimized for either high memory bandwidth, high memory depth or a combination of bandwidth and depth. The memory system is optimized by selecting appropriate memory devices 34 for inclusion in the memory module 20 and selecting a configuration for the bus structure 24 and conductive leads 38 formed on the substrate 36. Insofar as the data format selected is determined by the hardware design, is not possible to easily alter the data format. Instead, different memory modules must be used, a different motherboard in which the memory modules are normally inserted must be used, and a different memory controller must be used. Therefore, the data format is normally a fixed data format optimized for a particular application, even though the memory system may be called upon to operate in another application in which a different data format would be optimal. In such cases, the memory system cannot provide optimum performance.
There is therefore a need for a memory system that can have a variety of data formats each of which can be optimized to a specific application.